%0 Journal Article
%A 白创
%A 吕豪
%A 张伟
%T 	Design and verification of on-chip debug circuit based on JTAG

%D 2021
%R 10.19682/j.cnki.1005-8885.2021.0019
%J 中国邮电高校学报（英文）
%P 95-101
%V 28
%N 3
%X <p style="text-align:justify;">
	An on-chip debug circuit based on Joint Test Action Group (JTAG) interface for L-digital signal processor (L- DSP) is proposed, which has debug functions such as storage resource access, central processing unit (CPU) pipeline control, hardware breakpoint/ observation point, and parameter statistics. Compared with traditional debug mode, the proposed debug circuit completes direct transmission of data between peripherals and memory by adding data test-direct memory access (DT-DMA) module, which improves debug efficiency greatly. The proposed circuit was designed in a 0-18 μm complementary metal-oxide-semiconductor ( CMOS) process with an area of 167 234.76 μm<sup>2</sup> and a power consumption of 8.89 mW. And the proposed debug circuit and L-DSP were verified under a field programmable gate array (FPGA). Experimental results show that the proposed circuit has complete
</p>
<p style="text-align:justify;">
	debug functions and the rate of DT-DMA for transferring debug data is three times faster than the CPU.
</p>
%U https://jcupt.bupt.edu.cn/CN/10.19682/j.cnki.1005-8885.2021.0019