%0 Journal Article
%A Deng Junyong
%A Liu Yang
%A Tian Pu
%A Xie Xiaoyan
%T PPAA: a parallel primitive assembly accelerator in graphics processor
%D 2020
%R 10.19682/j.cnki.1005-8885.2020.1008
%J 中国邮电高校学报（英文）
%P 65-71
%V 27
%N 2
%X Primitive assembly is an inevitable procedure of graphics rendering which performs the objects preparation for the following steps, however, the conventional approaches suffer from some issues, such as the missing of surface attribute, mismatch of color mode for clipped primitives, and performance bottleneck of rendering pipeline. This paper takes all these issues into considerations, and proposes a parallel primitive assembly accelerator (PPAA) which can solve not only the functional problems but also improve the shading performance. The register transfer level (RTL) circuit is designed and the detailed approach is presented. The prototype systems are implemented on Xilinx field programmable gate array (FPGA) XC6VLX550T and Altera FPGA EP2C70F896C6. The experimental results show that PPAA can accomplish the assembly tasks correctly and with higher performance of 1.5x and 2.5x of two previous implementations. For the most frequently independent primitives, the PPAA can efficiently enhance the throughput by squeezing out the pipeline bubbles and by balancing the pipeline stages.
%U https://jcupt.bupt.edu.cn/CN/10.19682/j.cnki.1005-8885.2020.1008